1. Field of the Invention
This invention relates generally to the field of dielectric layers employed within microelectronics fabrications. More particularly, the invention relates to methods of fabrication of low dielectric constant dielectric layers employed within microelectronics fabrications.
2. Description of the Related Art
Fabrication of microelectronics devices makes effective use of patterned microelectronics conductor layers employed as interconnections for signal and power propagation by separating such conductor layers by means of blanket and/or patterned microelectronics dielectric layers. Advances in speed and performance requirements, along with decreases in dimensions and ground rules for microelectronics devices, have made the requirements placed upon such dielectric layers more stringent with respect to lowering the "relative dielectric constants" of the dielectric layers (i.e. the dielectric constants relative to vacuum). The "relative dielectric constant" of a dielectric layer is hereinafter referred to for brevity as the "dielectric constant" of the dielectric layer. Lower dielectric constant dielectric layers are desirable disposed between and around patterned microelectronics conductor layers within microelectronics fabrications since such lower dielectric constant dielectric layers typically provide microelectronics fabrications with reduced microelectronics fabrication parasitic capacitance and attenuated patterned microelectronics conductor layer cross-talk.
Conventional silicon containing dielectric layers formed of conventional silicon containing dielectric materials such as but not limited to silicon oxide dielectric materials, silicon nitride dielectric materials, and silicon oxynitride dielectric materials typically exhibit dielectric constants within the range of from about 4 to about 8 when formed disposed between and around patterned microelectronics conductor layers. While such conventional silicon containing dielectric layers formed employing conventional silicon containing materials formed by methods conventional in the art of microelectronics fabrication are satisfactory in general for electrically separating patterned microelectronics conductor layers, it is desirable to employ alternate methods and materials for forming dielectric layers having lower dielectric constants.
Of the methods and materials which may be employed for forming lower dielectric constant dielectric layers disposed between and around the patterns of patterned microelectronics conductor layers within microelectronics fabrications. methods which employ dielectric materials with intrinsically low dielectric constants are particularly desirable within the art of microelectronics fabrication. Such alternative low dielectric constant dielectric layers may be formed over microelectronics substrates by spin coating deposition of intrinsically low dielectric constant materials such as but not limited to organic polymer spin-on-polymer (SOP) dielectric materials. Such dielectric layers typically exhibit somewhat lower dielectric constants which range from about 2 to about 3. In particular, organic polymer spin-on-polymer (SOP) dielectric materials which may be employed for forming organic polymer spin-on-polymer (SOP) layers, include but are not limited to polyimide organic polymer spin-on-polymer dielectric materials, poly (arylene ether) organic polymer spin-on-polymer dielectric materials and fluorinated poly (arylene ether) organic polymer spin-on-polymer dielectric materials. Such spin-on-polymer (SOP) dielectric materials are typically thermally cured in order to form stable dielectric layers from the spin-on-polymer (SOP) dielectric materials.
The magnitude of the dielectric constant as well as the stability of the physical and chemical properties of the spin-on-polymer (SOP) dielectric layer are often determined by the degree of polymerization and the amount of H2O and --OH in the polymer dielectric layer. Conventional curing processes for organic polymer dielectric layers as are employed in the art of microelectronics fabrication employ elevated temperatures and often a vacuum environment (i. e. sub-atmospheric pressure) to facilitate these objectives
Although desirable for having relatively lower dielectric constant values, spin-on-polymer (SOP) dielectric materials which are employed for forming spin-on-polymer (SOP) dielectric layers in microelectronics fabrications are not without problems. In particular, curing of spin-on-polymer (SOP) dielectric layers often results in variable dimensional and mechanical changes of SOP layers, which dimensional and mechanical changes are often significant and difficult to control, particularly if subsequent processing of the microelectronics fabrication within which such spin-on-polymer (SOP) dielectric layers are employed requires additional exposure to conditions where additional changes similar to those experienced in curing of the polymer dielectric layer can take place. Likewise, degradative changes in physical and chemical properties of low dielectric constant dielectric layers employed within microelectronics fabrications during the service life usage of such fabrications is particularly troublesome if such tendency towards further change is not attenuated.
It is therefore towards the goal of forming within microelectronics fabrications low dielectric constant dielectric layers formed from spin-on-polymer (SOP) dielectric materials, while forming the low dielectric constant dielectric layers with stabilized physical and chemical properties, that the present invention is more generally directed.
Various methods and associated microelectronics structures have been disclosed within the art of microelectronics fabrication for formings upon and around patterned microelectronics conductor layers low dielectric constant organic polymer dielectric layers within microelectronics fabrications.
For example, Havemann, in U.S. Pat. No. 5,565,384, discloses a self-aligned method for forming an interconnection via through a blanket silicon containing dielectric layer, to access a patterned conductor layer having formed disposed between and around its pattern a low dielectric constant dielectric layer. The blanket low dielectric constant dielectric layer is formed from an organic polymer spin-on-polymer (SOP) dielectric material which functions as an etch stop layer for plasma etching, as well as constituting a low dielectric constant dielectric material for forming the low dielectric constant dielectric layer within a microelectronics fabrication.
Further, Chang, in U.S. Pat. No. 5,559,055, discloses a method for forming low dielectric constant dielectric layers disposed between and around patterns of patterned microelectronics conductor layers within a microelectronics fabrication. The method employs selective subtractive etch of a conventional silicon containing interlevel dielectric layer to provide an air gap which may optionally be backfilled with spinon-polymer (SOP) dielectric material. This result is achieved with air gap (dielectric constant 1.0) or alternatively with organic polymer material (dielectric constant from about 2.2 to about 3.4) to reduce capacitance and hence the resistance-capacitance (RC) time constant resulting in faster device speed.
Desirable in the art of microelectronics fabrication are additional methods and materials which may be employed for forming a dielectric layer with a relatively low dielectric constant disposed between and around a patterned microelectronics conductor layer within a microelectronics fabrication, where the low dielectric constant dielectric layer is cured so as to be able to withstand subsequent processing as is conventional in the state of the art of microelectronics fabrication without substantial alteration of dimensions and other physical and chemical properties.
It is towards the foregoing goals that the present invention is both generally and more specifically directed.